Thermal expansion testing of semiconductor silicon carbide (SiC) substrates determines the coefficient of thermal expansion (CTE) along the crystallographic a- and c-axes, providing essential data for epitaxial growth, wafer fabrication, and power device packaging. Accredited third-party laboratories perform these measurements using push-rod dilatometry, thermomechanical analysis, and interferometric techniques in accordance with standards such as ASTM E228, ASTM E831, ASTM E289, ISO 11359, and ISO 17562. This article describes the sample requirements, testing items, measurement methods, and engineering applications of SiC substrate expansion performance evaluation.
Technical Overview
Silicon carbide (SiC) is a wide-bandgap compound semiconductor that has become the substrate material of choice for high-voltage power devices, radio-frequency (RF) electronics, and advanced optoelectronics, owing to its high critical breakdown field, excellent thermal conductivity, and outstanding thermal and chemical stability. Because SiC devices are fabricated, packaged, and operated across temperatures ranging from room temperature to junction temperatures above 250 °C, with process steps such as implantation activation anneals exceeding 1500 °C, the thermal expansion behavior of the substrate directly governs epitaxial film stress, wafer geometry drift, die-attach integrity, and long-term module reliability.
Both 4H-SiC and 6H-SiC, the dominant polytypes used in industry, crystallize in the hexagonal crystal system. Their thermal expansion is therefore anisotropic: the expansion coefficient along the in-plane a-axis directions differs measurably from that along the c-axis, which is parallel to the wafer normal. Reported reference values are approximately 3.1–3.5 × 10⁻⁶ /K along the a-axis and 3.7–4.3 × 10⁻⁶ /K along the c-axis near room temperature, rising to roughly 4.5–5.5 × 10⁻⁶ /K when expressed as a mean coefficient referenced to 1000 °C. Because these values are small, accurate measurement demands instrumentation with nanometer-level displacement resolution, rigorous calibration, and careful control of atmosphere and temperature uniformity.
Two coefficients are conventionally reported. The mean coefficient of thermal expansion over a temperature interval T1 to T2 is defined as αm = (L2 − L1) / (L0 × (T2 − T1)), where L0 is the specimen length at the reference temperature, while the instantaneous (differential) coefficient is α(T) = (1/L) × (dL/dT). Accredited third-party laboratories deliver both values, together with the full dilation curve, hysteresis behavior, and a documented measurement uncertainty, ensuring the data are traceable and suitable for design, qualification, and supplier specification purposes.
Testing Samples
4H-SiC Single-Crystal Substrates
These are the most widely submitted samples and include n-type conductive wafers (nitrogen-doped, resistivity typically 0.015–0.025 Ω·cm) for power MOSFETs and Schottky diodes, as well as semi-insulating wafers (high-purity or deep-level doped, resistivity ≥ 10⁵ Ω·cm) for RF applications. Common formats are 100 mm, 150 mm, and 200 mm diameters with thicknesses of approximately 350–500 μm, either on-axis or with a 4° off-cut toward the <11-20> direction. Both epi-ready polished wafers and as-sliced bulk substrates can be evaluated.
6H-SiC Single-Crystal Substrates
Although less common than 4H material, 6H-SiC substrates remain in use for specialized RF, sensor, and legacy optoelectronic applications. The expansion characterization approach is identical, but reported coefficients must clearly identify the polytype because the stacking sequence produces a slightly different temperature dependence.
Machined Dilatometry Coupons
Bulk expansion instruments require rectangular bar specimens, typically 20–25 mm long, 3–5 mm wide, and 1–3 mm thick, cut from wafers or boule sections. In-plane (a-axis) specimens are oriented with the long axis along <11-20> or <1-100>, while c-axis specimens are machined with the long axis parallel to [0001]. Where destructive sampling of full wafers is not permitted, stacked wafer segments or interferometric and X-ray methods applied to intact wafers may be used instead.
Sample Preparation and Pretreatment
Coupon faces must be lapped or ground flat and mutually parallel, since face non-parallelism is a major source of low-expansion measurement error. A stress-relief cleaning and, where specified, a conditioning anneal are recommended to remove machining-induced residual stress. The reference length at 23 °C is measured with a calibrated micrometer or length gauge, and the crystallographic orientation of each specimen is laser-marked or documented before testing.
Testing Items
Standard expansion performance evaluation of SiC substrates typically covers the following items, with the temperature range and atmosphere tailored to the client's specification:
- Mean linear coefficient of thermal expansion over defined intervals, for example 25–200 °C, 25–500 °C, 25–800 °C, or 25–1000 °C.
- Instantaneous (differential) CTE as a continuous function of temperature across the programmed range.
- Anisotropic expansion coefficients α(a-axis) and α(c-axis) for hexagonal 4H and 6H polytypes.
- Complete fractional length-change curve ΔL/L0 versus temperature for both heating and cooling segments.
- Thermal expansion hysteresis between heating and cooling branches, and residual permanent dimensional change after one or multiple thermal cycles.
- Repeatability assessment over consecutive cycles to verify dimensional stability.
- Optional full-wafer high-temperature bow and warp evolution, evaluated by non-contact optical profilometry where packaging-related geometry stability is of concern.
- Measurement uncertainty budget and metrological traceability statement for all reported values.
Testing Methods
Push-Rod Dilatometry (ASTM E228, ISO 17562, JIS R 1618)
Push-rod dilatometry is the primary method for SiC coupon evaluation. The specimen is placed in a furnace tube and contacted by a low-expansion fused-silica or alumina rod; the thrust is transmitted to a high-resolution LVDT or capacitive displacement sensor. Testing is typically performed at 3–5 K/min under static high-purity argon or nitrogen to suppress surface oxidation above approximately 600 °C. Runs are corrected using an empty-holder baseline and a certified reference material such as sapphire or fused silica traceable to a national metrology institute. The method covers room temperature to 1000–1200 °C and achieves relative CTE uncertainties on the order of 3–5% for low-expansion ceramics when properly executed.
Thermomechanical Analysis, TMA (ASTM E831, ISO 11359)
TMA uses a compact furnace and a quartz or alumina probe with programmable loading, allowing smaller specimens (2–10 mm) and faster turnaround. It is well suited to routine quality-control screening of incoming substrates and to comparisons between wafer lots, over ranges from room temperature to approximately 500–800 °C. Because specimen geometry is smaller, TMA results are generally cross-checked against push-rod dilatometry when reference-grade accuracy is required.
Absolute Laser Interferometry (ASTM E289)
Interferometric dilatometry measures specimen expansion directly as an optical path change, providing nanometer displacement resolution without mechanical contact. It delivers the lowest available uncertainty for low-expansion materials and is used for reference measurements, arbitration between conflicting data sets, and calibration-chain support for other instruments.
High-Temperature X-Ray Diffraction
HT-XRD tracks the lattice parameters a and c as a function of temperature, yielding the crystallographic expansion coefficients of both axes non-destructively on intact wafer pieces. It is the preferred complementary technique when a-axis and c-axis coefficients must be separated without machining c-axis bars from boule material.
Calibration, Atmosphere, and Data Evaluation
Regardless of the technique, temperature sensors are calibrated at fixed points, instrument expansion is subtracted via reference-material runs, and mean coefficients are computed from the corrected dilation curves. The final report states the polytype, crystallographic orientation, specimen dimensions, atmosphere, heating rate, temperature program, ΔL/L0 curves, tabulated mean CTE values with their intervals, and the expanded measurement uncertainty, ensuring full compliance with client specifications and with the relevant ASTM, ISO, IEC, or GB/JIS documentary standards.
Applications
Expansion data for SiC substrates are used throughout the semiconductor value chain:
- Epitaxy process design: quantifying thermal-mismatch stress and post-growth wafer bow in 4H-SiC homoepitaxy and GaN-on-SiC heteroepitaxy, where differences between layer and substrate CTE drive crack risk and dislocation generation.
- Wafer fabrication: verifying dimensional and geometric stability through oxidation, activation annealing, and metallization sintering steps that span hundreds to thousands of degrees.
- Power module packaging: selecting die-attach materials (solder, silver sintering) and ceramic insulating substrates whose expansion behavior minimizes shear strain at interfaces with SiC dies, whose CTE near 4 × 10⁻⁶ /K contrasts sharply with copper at approximately 17 × 10⁻⁶ /K.
- Reliability engineering: supplying CTE inputs for thermal-cycling and power-cycling lifetime models and for finite-element simulation of modules qualified under IEC 60747 and IEC 60749 test frameworks.
- Materials research and development: comparing polytypes, evaluating doping and defect effects on expansion, and generating reference data for new crystal-growth processes.
- Supplier qualification and incoming inspection: providing an objective, standards-based acceptance criterion for substrate procurement between crystal growers and device manufacturers.
FAQ
Why is thermal expansion testing so important for SiC substrates?
SiC devices routinely experience severe thermal excursions during fabrication and service. Small differences in expansion between the substrate, epitaxial layers, die-attach, and package materials accumulate as stress and fatigue with every thermal cycle, so accurate CTE data are essential for yield control, package design, and lifetime prediction.
What are the typical CTE values for 4H-SiC?
Near room temperature the a-axis coefficient is approximately 3.2 × 10⁻⁶ /K and the c-axis coefficient approximately 3.7–4.0 × 10⁻⁶ /K. Mean coefficients referenced to 1000 °C typically fall between 4.5 and 5.5 × 10⁻⁶ /K. Exact values depend on polytype, temperature interval, and measurement method, which is why standardized reporting of the reference temperature is mandatory.
What specimen size is required?
Push-rod dilatometry generally requires bars of 20–25 mm length; TMA can work with 2–10 mm specimens. If destructive cutting of wafers is not acceptable, interferometric or X-ray methods on intact wafer pieces can be arranged through accredited third-party laboratories.
What temperature range can be covered?
Routine testing spans room temperature to 500–1000 °C, and push-rod systems can extend to approximately 1200 °C under inert atmosphere. Higher-temperature requirements should be discussed with the laboratory because SiC surface stability and fixture compatibility become limiting factors.
How is the anisotropy of hexagonal SiC handled?
Separate specimens are machined with their long axes parallel to the in-plane a-direction and to the c-axis [0001], respectively, so that α(a) and α(c) are measured independently. Alternatively, high-temperature XRD extracts both lattice-direction coefficients from a single wafer sample.
Which method should be selected for a given project?
Push-rod dilatometry (ASTM E228 / ISO 17562) is the default for reference-grade coupon data; TMA (ASTM E831 / ISO 11359) suits fast lot screening; interferometry (ASTM E289) is reserved for the lowest-uncertainty or arbitration needs. Laboratories typically advise on method selection based on sample availability, target range, and required uncertainty.
What atmosphere is used during testing?
Static or flowing high-purity argon or nitrogen is standard above approximately 600 °C to prevent oxidation of silicon carbide surfaces, which would otherwise distort the measured dilation. Ambient air testing is possible for moderate temperatures when explicitly specified.
How long does a typical test take?
Single-cycle dilatometry with calibration runs is usually completed within several working days, while multi-cycle, multi-orientation, or interferometric programs may require additional time. Accredited third-party laboratories provide formal quotes, sample-preparation instructions, and reporting formats before testing begins.